Using LSS adaptor board with serial communication software

@Eranda43 oh! I totally forgot to respond to this amazing reply you placed! My bad! :thinking:

I’m glad this was helpful! We are certainly very interested in improving all aspect of the LSS products, so feel free to get back to us with any other ideas/comments/etc.! We’ll do our best to either clarify stuff or improve it as much as we can.

Thanks for that! I’m sure the rest of the community will appreciate your efforts!

Here are some ideas concerning what you found out about all of this:

I’ve only really had the issue (on Windows) with reading from the buffer, not writing to it (and therefore to the LSS bus). That being said, it may be handled differently on various Linux platforms.

Yes, there can always be some extra latency just from the fact that if you are not running a RTOS then anything can happen, delaying a reply from the hardware/drivers.

And, of course, even if your packet exceeds the size of the buffer, the extra bytes may be delayed until the next buffer timeout (though that was not my experience with PC TX > LSS RX).

Another option (at least for PC TX) might be to simply tell the UART drivers to flush out the data (instead of waiting for exact size/timeout).

As for replies, it may be possible to add a configuration to the LSS firmware to add padding to replies. When running at 500k baud (~20 µs / character) the delay from buffer timeout/drivers/OS HAL is far, far longer (sometimes dozens of ms) compared to adding a few characters to each reply. It would have to be tested, but that may be one way to circumvent the issue. Since whitespace is ignored in the LSS protocol that would be an easy way to add padding (such as at the end before the footer; a carriage return).

With a lot of hardware (and proper drivers) you can reconfigure the buffering to be different. By default, they are usually set to 8-16 bytes to cater to high-data rates instead of low latency (optimally every byte would trigger an interrupt!). So that should be an interesting thing to look into. I know many of the FTDI chips (such as the one used in the LSS Adapter Board) have configurations that can be changed to lower latency.

I assume that package is probably changing the chip’s/drivers settings to improve the latency. Since the data rate for LSS is quite low but we want high latency smaller buffers are definitely a good way to go. And if you don’t have much running simultaneously anyway and multi cores than it is a no-brainer to do so.

I’ll have to look into that package and see what I can find out about it. I personally mostly run Arch or arch-based systems (such as Manjaro).

Well, other than changing settings in the chip/its drivers, I’m not sure if there is anything else to do. To be investigated too! :slight_smile:

This seems like it would be quite acceptable for most cases.

We do have some customers using the LSS bus with a RPi4. The big advantage there is that the RPi4 has multiple physical UART buses available (of course, you’ll need a level shifter / voltage translator such as RB-Spa-879 to use them with the LSS). You can change the FIFO size on some of those buses. If I remember correctly, some can be set to 1 byte and then all that’s left is to give it high priority and you’ll be near real-time. Also, since there are multiple buses available, you can set each UART for a group of LSS to keep everything fast.

@cmackenzie has been doing some great work on this recently. You can read some of the details about it here. Be careful, it is a long topic full of very interesting discussions… you may get sucked in so make sure you have a handy snack nearby! :smiley:

Keep up the good work @Eranda43! :slight_smile: :+1:

Sincerely,