hi there
I got a problem with simulation … I am doing a simulation for PN code generator and I wrote the sketch for it
I will go for small explanation to make the problem clear
1- PN generator:
This component implements 7-bit PN code generator using three stages Linear Feedback
Shift Register (LFSR).
The Two separate PN generator entities were implemented, one each for two sources. The 3-bit initializer (seed) was set within the VHDL coding itself in each entity. The PN generator for Source 1 is initialized with (S2 S1 S0) = 111 and generates PN code 1110100 whereas the PN generator for Source 2 is initialized with (S2 S1 S0) = 110 and generates PN code1101001.
so I create two inputs one is( CLOCK ) and the other is (INIT) and the output is (PNCODE)
after that I enter the simulation windows
for CLOCK input I right click than select ( Force Clock ) than I give 1 for ( Leading edge value ) and 0 for Trailing edge value and 100 ns for (period)
for INIT input I right click than select ( Force Constant ) than I give 0 for ( Force to value )
the problem is the output (PNCODE) is still Undefined and it give no thing even after running the simulation
please help … I attach the files and sketchs
pncode.rar (1.42 MB)