moon’s recent post about a digital logic sumo bot has inspired me to start yet another project.
I’m now almost finished with the schematic for the bot, but upon reviewing it, I’m not sure if I’m understanding a certain situation correctly.
This might be a dumb question, but I don’t currently have any logic devices handy to test it.
My $130 Digital & Microcontroller textbook (though a HUGE help otherwise) doesn’t seem to explain it, either.
f5.putfile.com/thumb/8/24111474361.jpg
In the above schematic, I’ve happened upon a scenario in which I wish to control another logic device with a 3-state, active-LOW buffer.
The idea is to overide signals sent by certain low-priority sensors with signals from the higher-priority sensors.
The first circuit shows the way that I understand the buffer to work.
However, in the other example, I’m confused.
I know that a 1 on the buffer-enable input will disable the buffer, leaving the output floating (i.e. no connection).
After that, though, when the floating line is input into something like an OR that already has it’s necessary 1 input satisfied, will the output of the OR be floating or a 1?
In other words, does it matter if some of the OR’s input pins aren’t connected, so long as there’s at least a single 1 input?
Or do logic gates demand that every input be satisfied with either a 1 or a 0?
I agree that it would be a good idea to tie a pull down (or up for AND gates) resistor the the input that can be left floating. If you are using CMOS logic parts it is pretty much a requirement to pull up or down any unused or otherwise floating inputs. TTL or LSTTL stuff generally floats unused inputs high but you can’t guarantee it with every chip and it’s also fairly noise sensitive (relaltive to being actively driven or pulled.)
Oh dear…
Well, the idea wasn’t to get rid of the float.
I actually wanted it.
I had been hoping that a floating input could be used to nullify everything after it.
So those darn trixy little buggers would take a guess as to what it would be rather than just stop working.
Great.
Now I get to scrap my entire setup.
What would happen with scenario like a floating input getting stuck into a transistor base?
I’m guessing it would not turn on the transistor… but now I’m not so sure…
Does the whole float-guessing thing happen with all standard logic devices (specifically INVERTs)?
(Please tell me no. )
Digital logic only has two valid states Nick, 1 and 0. The intent of a tri-state or high impedance output is to allow multiple devices to share a common wire. TTL logic tends to flot unconnected inputs to a high state because of the way the input transistors are biased. CMOS logic needs to have unused inputs pulled to power or ground because they have very high input impedances and the absolute worsts thing you can do to a CMOS circuit is “float” its input somewhere between a definite 1 or 0 because they bias BOTH the source and sink output transistors at the SAME time… lots of current, lots of electrical noise, sometimes you get the magic smoke thing, generally speaking not a healthy situation for your IC.
What are you trying to accomplish that you can not express it in logic without some “fuzzy” indeterminate state?
DOH!
I just realized…
What you said about the pulldown/up resistor will actually work here, if I rearange things.
Thanks!!!
Here’s what I was trying to do, which (except for the H-Bridge) won’t work.
Thankfully, I usually think out my thought process on the edge of the schematic (or in the comments, when programming), so I don’t have to try to explain it from memory:
Oh, and moon, no peeking!
I’ve been sitting here doing a bit of light bedtime reading (a hundred pages or so in a textbook ) and I happened upon the S-R flipflop.
I’ll have to reread this again, but, from looking at it’s logic table, I think I can just tie the RESET input low and tie Q into the FWD and Q(inverted) into the BACK.
Then when I send a 1 to the SET, it turns the motors off (both Q’s = 0) and when I send a 0 to the SET, it turns Q (hooked to FWD) high and leaves Q(inverted) low.
And, as for overiding those sensors with the higher-priority sensors (the floor sensors), I can just stick another transistor across all 4 H-bridge connections and use that to directly disable them.
That reminds me…
Can anyone recommend a nice low-current transistor?
I’ve been hunting, but even those in the TO-92 package seem beefy.
Or, is there any simple way to assist the logic devices in driving them?
Perhaps just tying a pullup into the base of those that will normally be on (and vice versa for those normally off)?
The circuit isn’t currently big enough to worry much about fanout issues, but I’m a worrier, especially when I can’t get my nice fifty-foot overkill clearance.
Both Q’s will never be high - they are always the inverse of each other.
Also, doing a 0 on the SET doesn’t change anything - doing a 1 on the SET turns on Q, and doing a 1 on the RESET turns on Q-not.
If he is using the not-allowed state of a NOR type S-R latch he can get both Q and \Q to go active. It doesn’t seem like the concept of a Set-Reset “latch” has sunk in thoroughly yet though.
Aye, I had been planning on cheating with the “not allowed” state.
I have read, reread, rereread (and a few more iterations of that), and do now understand the real purpose of the flip-flop as a latching device.
Still, though, I’m not one to worry about how things are supposed to be used so long as the way that I use them works.
Digital logic gurus can bite me when I get my sumo whizzing around the ring.
)