RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The RISC-V ISA is provided under open source licenses that do not require fees to use. SiFive's Freedom E310 is the first member of the Freedom Everywhere family of customizable SoCs. Designed for microcontroller, embedded, IoT, and wearable applications, the FE310 features SiFive s E31 CPU Coreplex, a high-performance, 32-bit RV32IMAC core. Running at 320+ MHz, the processor is among the fastest microcontrollers in the market. SiFive has also released the RTL (register-transfer level) code for Freedom E310 under an open source license that will allow chip designers to customize their own SoC on top of the base FE310.
A Linux development or virtual machine is needed to compile the processor, generate the bitstream and upload applications to the processor and install the following packages
Step through the tutorial “Running a RISC-V Processor on the Arty A7” and load the FE310 on Digilent Arty A7-100T. Once this is completed, the ARTY 100T will be running the RISC-V processor. You can confirm this by pressing the following
Develop different custom applications on Arduino IDE. Debug the program through Olimex JTAG pod. All you need is to connect the JTAG pod to the Arty A7's Pmod Port D.