#Build: Synplify Pro K-2015.09L-2, Build 126R, Dec 14 2015
#install: C:\lscc\diamond\3.7_x64\synpbase
#OS: Windows 8 6.2
#Hostname: NTB-ZABRSA

# Sat Sep 03 17:32:08 2016

#Implementation: PlotterV3_Imp

Synopsys HDL Compiler, version comp201509p1, Build 145R, built Dec  9 2015
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

Synopsys Verilog Compiler, version comp201509p1, Build 145R, built Dec  9 2015
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@N: :  | : Running Verilog Compiler in System Verilog mode 
@N: :  | : Running Verilog Compiler in Multiple File Compilation Unit mode 
@I::"C:\lscc\diamond\3.7_x64\synpbase\lib\lucent\machxo.v"
@I::"C:\lscc\diamond\3.7_x64\synpbase\lib\lucent\pmi_def.v"
@I::"C:\lscc\diamond\3.7_x64\synpbase\lib\vlog\hypermods.v"
@I::"C:\lscc\diamond\3.7_x64\synpbase\lib\vlog\umr_capim.v"
@I::"C:\lscc\diamond\3.7_x64\synpbase\lib\vlog\scemi_objects.v"
@I::"C:\lscc\diamond\3.7_x64\synpbase\lib\vlog\scemi_pipes.svh"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Main.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\timeRX.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\timeTX.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\uartRX.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\uartTX.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Stepper.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PWM.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\StepperTime.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Mikrosecond.v"
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module Main
@N:CG364 : machxo.v(1372) | Synthesizing module OSCC.

@N:CG364 : timeRX.v(1) | Synthesizing module TimeRX.

@N:CL189 : timeRX.v(7) | Register bit c_delay[13] is always 0.
@N:CL189 : timeRX.v(7) | Register bit c_delay[12] is always 0.
@N:CL189 : timeRX.v(7) | Register bit c_delay[11] is always 0.
@N:CL189 : timeRX.v(7) | Register bit c_delay[10] is always 0.
@W:CL279 : timeRX.v(7) | Pruning register bits 13 to 10 of c_delay[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CG364 : uartRX.v(1) | Synthesizing module UartRX.

@N:CL189 : uartRX.v(13) | Register bit index[4] is always 0.
@N:CL189 : uartRX.v(13) | Register bit index[5] is always 0.
@N:CL189 : uartRX.v(13) | Register bit index[6] is always 0.
@N:CL189 : uartRX.v(13) | Register bit index[7] is always 0.
@W:CL279 : uartRX.v(13) | Pruning register bits 7 to 4 of index[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CG364 : StepperTime.v(1) | Synthesizing module StepperTime.

@N:CG364 : Stepper.v(1) | Synthesizing module Stepper.

@N:CG364 : Main.v(1) | Synthesizing module Main.

@W:CG360 : Main.v(4) | Removing wire sgnServo, as there is no assignment to it.
@W:CL118 : Main.v(36) | Latch generated from always block for signal targetY[7:0]; possible missing assignment in an if or case statement.
@W:CL118 : Main.v(36) | Latch generated from always block for signal targetX[7:0]; possible missing assignment in an if or case statement.
@W:CL157 : Main.v(4) | *Output sgnServo has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@N:CL159 : Main.v(3) | Input btnReset is unused.
@N:CL189 : StepperTime.v(7) | Register bit c_delay[18] is always 0.
@N:CL189 : StepperTime.v(7) | Register bit c_delay[19] is always 0.
@N:CL189 : StepperTime.v(7) | Register bit c_delay[20] is always 0.
@N:CL189 : StepperTime.v(7) | Register bit c_delay[21] is always 0.
@N:CL189 : StepperTime.v(7) | Register bit c_delay[22] is always 0.
@W:CL279 : StepperTime.v(7) | Pruning register bits 22 to 18 of c_delay[22:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Sep 03 17:32:08 2016

###########################################################]
Synopsys Netlist Linker, version comp201509p1, Build 145R, built Dec  9 2015
@N: :  | Running in 64-bit mode 
File C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Sep 03 17:32:08 2016

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Sep 03 17:32:08 2016

###########################################################]
Synopsys Netlist Linker, version comp201509p1, Build 145R, built Dec  9 2015
@N: :  | Running in 64-bit mode 
File C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\synwork\PlotterV3_Imp_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Sep 03 17:32:10 2016

###########################################################]
Pre-mapping Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1368R, Built Jan  8 2016 09:37:50
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version K-2015.09L-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

Linked File: PlotterV3_Imp_scck.rpt
Printing clock  summary report in "C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\PlotterV3_Imp_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)

@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=3  set on top level netlist Main

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)



Clock Summary
*****************

Start                               Requested     Requested     Clock                                          Clock                
Clock                               Frequency     Period        Type                                           Group                
------------------------------------------------------------------------------------------------------------------------------------
Main|count_derived_clock[0]         1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Autoconstr_clkgroup_0
Main|osc_clk_inferred_clock         1.0 MHz       1000.000      inferred                                       Autoconstr_clkgroup_0
StepperTime_0|tmr_derived_clock     1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Autoconstr_clkgroup_0
StepperTime_1|tmr_derived_clock     1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Autoconstr_clkgroup_0
TimeRX|tmrRX_derived_clock          1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Autoconstr_clkgroup_0
UartRX|isBusy_derived_clock         1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Autoconstr_clkgroup_0
====================================================================================================================================

@W:MT529 : timerx.v(7) | Found inferred clock Main|osc_clk_inferred_clock which controls 49 sequential elements including uartRX1.timeRX1.c_delay[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N:MO111 : main.v(4) | Tristate driver sgnServo (in view: work.Main(verilog)) on net sgnServo (in view: work.Main(verilog)) has its enable tied to GND.

Available hyper_sources - for debug and ip models
	None Found

None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 140MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Sep 03 17:32:11 2016

###########################################################]
Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 1368R, Built Jan  8 2016 09:37:50
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version K-2015.09L-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N:MO111 : main.v(4) | Tristate driver sgnServo (in view: work.Main(verilog)) on net sgnServo (in view: work.Main(verilog)) has its enable tied to GND.

Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 
@N:FX493 :  | Applying initial value "0001" on instance stepperY.state[3:0]  
@N:FX493 :  | Applying initial value "0001" on instance stepperY.state[3:0]  
@N:FX493 :  | Applying initial value "00000000" on instance targetY[7:0]  
@N:FX493 :  | Applying initial value "00000000" on instance targetX[7:0]  

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N: : stepper.v(17) | Found updn counter in view:work.Stepper_1(verilog) inst curr[7:0] 
@W:MO129 : stepper.v(17) | Sequential instance stepperX.target[8] reduced to a combinational gate by constant propagation
@W:MO129 : stepper.v(17) | Sequential instance stepperX.target[9] reduced to a combinational gate by constant propagation
@W:MO129 : stepper.v(17) | Sequential instance stepperX.target[10] reduced to a combinational gate by constant propagation
@W:MO129 : stepper.v(17) | Sequential instance stepperX.target[11] reduced to a combinational gate by constant propagation
@W:MO129 : stepper.v(17) | Sequential instance stepperX.target[12] reduced to a combinational gate by constant propagation
@W:MO129 : stepper.v(17) | Sequential instance stepperX.target[13] reduced to a combinational gate by constant propagation
@W:MO129 : stepper.v(17) | Sequential instance stepperX.target[14] reduced to a combinational gate by constant propagation
@W:MO129 : stepper.v(17) | Sequential instance stepperX.target[15] reduced to a combinational gate by constant propagation
@N:MF179 : stepper.v(14) | Found 16 bit by 16 bit '==' comparator, 'un3_isBusy'
@N: : stepper.v(17) | Found updn counter in view:work.Stepper_0(verilog) inst curr[7:0] 
@W:MO129 : stepper.v(17) | Sequential instance stepperY.target[0] reduced to a combinational gate by constant propagation
@W:MO129 : stepper.v(17) | Sequential instance stepperY.target[11] reduced to a combinational gate by constant propagation
@W:MO129 : stepper.v(17) | Sequential instance stepperY.target[12] reduced to a combinational gate by constant propagation
@W:MO129 : stepper.v(17) | Sequential instance stepperY.target[13] reduced to a combinational gate by constant propagation
@W:MO129 : stepper.v(17) | Sequential instance stepperY.target[14] reduced to a combinational gate by constant propagation
@W:MO129 : stepper.v(17) | Sequential instance stepperY.target[15] reduced to a combinational gate by constant propagation
@N:MF179 : stepper.v(14) | Found 16 bit by 16 bit '==' comparator, 'un3_isBusy'

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB)

@N:FA113 : stepper.v(46) | Pipelining module target_2[15:0]
@N:MF169 : stepper.v(17) | Register target[15:0] pushed in.
@N:MF169 : main.v(36) | Register targetY[7:0] pushed in.
@N:MF169 : uartrx.v(13) | Register data[7:0] pushed in.
@N:MF169 : main.v(29) | Register count[0] pushed in.
@N:MF169 : uartrx.v(13) | Register buffer[7:0] pushed in.
@N:MF169 : main.v(36) | Register targetX[7:0] pushed in.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 141MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 141MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -4.53ns		 128 /       163
   2		0h:00m:01s		    -4.53ns		 128 /       163
   3		0h:00m:01s		    -4.53ns		 128 /       163
   4		0h:00m:01s		    -4.53ns		 128 /       163
   5		0h:00m:01s		    -4.53ns		 128 /       163
   6		0h:00m:01s		    -4.53ns		 128 /       163
@N:FX271 :  | Instance "uartRX1.target_pipe_2" with 9 loads replicated 1 times to improve timing  
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication

   7		0h:00m:02s		    -4.35ns		 128 /       164
   8		0h:00m:02s		    -4.35ns		 128 /       164
   9		0h:00m:02s		    -4.35ns		 128 /       164
  10		0h:00m:02s		    -4.35ns		 128 /       164


  11		0h:00m:02s		    -4.35ns		 128 /       164
  12		0h:00m:02s		    -4.35ns		 128 /       164
  13		0h:00m:02s		    -4.35ns		 128 /       164
  14		0h:00m:02s		    -4.35ns		 128 /       164
  15		0h:00m:02s		    -4.35ns		 128 /       164

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 142MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
@N:MO111 : main.v(4) | Tristate driver sgnServo_obuft.un1[0] (in view: work.Main(verilog)) on net sgnServo (in view: work.Main(verilog)) has its enable tied to GND.

Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 142MB)

@N:MT611 :  | Automatically generated clock StepperTime_0|tmr_derived_clock is not used and is being removed 
@N:MT611 :  | Automatically generated clock StepperTime_1|tmr_derived_clock is not used and is being removed 
@N:MT611 :  | Automatically generated clock TimeRX|tmrRX_derived_clock is not used and is being removed 
@N:MT611 :  | Automatically generated clock UartRX|isBusy_derived_clock is not used and is being removed 
@N:MT611 :  | Automatically generated clock Main|count_derived_clock[0] is not used and is being removed 


@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 164 clock pin(s) of sequential element(s)
0 instances converted, 164 sequential instances remain driven by gated/generated clocks

================================================================================================= Gated/Generated Clocks =================================================================================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance     Explanation                                                                                                                   
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        OSCC_1              OSCC                   164        count[0]            Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
==========================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 109MB peak: 142MB)

Writing Analyst data base C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\synwork\PlotterV3_Imp_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 140MB peak: 142MB)

Writing EDIF Netlist and constraint files
@N:FX1056 :  | Writing EDF file: C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\PlotterV3_Imp.edi 
K-2015.09L-2
@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 144MB peak: 146MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 143MB peak: 146MB)

@W:MT420 :  | Found inferred clock Main|osc_clk_inferred_clock with period 11.54ns. Please declare a user-defined clock on object "n:osc_clk" 


##### START OF TIMING REPORT #####[
# Timing Report written on Sat Sep 03 17:32:15 2016
#


Top view:               Main
Requested Frequency:    86.6 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 



Performance Summary
*******************


Worst slack in design: -0.861

                                Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                  Frequency     Frequency     Period        Period        Slack      Type         Group                
-------------------------------------------------------------------------------------------------------------------------------------
Main|osc_clk_inferred_clock     86.6 MHz      80.6 MHz      11.545        12.406        -0.861     inferred     Autoconstr_clkgroup_0
=====================================================================================================================================





Clock Relationships
*******************

Clocks                                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting                     Ending                       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------------
Main|osc_clk_inferred_clock  Main|osc_clk_inferred_clock  |  11.545      -0.861  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: Main|osc_clk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                               Starting                                                                   Arrival           
Instance                       Reference                       Type        Pin     Net                    Time        Slack 
                               Clock                                                                                        
----------------------------------------------------------------------------------------------------------------------------
uartRX1.target_pipe_2_fast     Main|osc_clk_inferred_clock     FD1P3AX     Q       target_pipe_2_fast     1.552       -0.861
uartRX1.target_pipe_2          Main|osc_clk_inferred_clock     FD1P3AX     Q       countf[0]              1.672       -0.853
uartRX1.target_pipe            Main|osc_clk_inferred_clock     FD1P3AX     Q       target_pipe            1.456       -0.765
uartRX1.target_pipe_1          Main|osc_clk_inferred_clock     FD1P3AX     Q       dataRXf[0]             1.456       -0.765
uartRX1.target_pipe_3          Main|osc_clk_inferred_clock     FD1P3AX     Q       target_pipe_3          1.348       -0.657
uartRX1.target_pipe_4          Main|osc_clk_inferred_clock     FD1P3AX     Q       dataRXf[1]             1.348       -0.657
uartRX1.target_pipe_6          Main|osc_clk_inferred_clock     FD1P3AX     Q       target_pipe_6          1.348       -0.657
uartRX1.target_pipe_7          Main|osc_clk_inferred_clock     FD1P3AX     Q       dataRXf[2]             1.348       -0.657
uartRX1.target_pipe_9          Main|osc_clk_inferred_clock     FD1P3AX     Q       target_pipe_9          1.348       -0.529
uartRX1.target_pipe_10         Main|osc_clk_inferred_clock     FD1P3AX     Q       dataRXf[3]             1.348       -0.529
============================================================================================================================


Ending Points with Worst Slack
******************************

                      Starting                                                             Required           
Instance              Reference                       Type        Pin     Net              Time         Slack 
                      Clock                                                                                   
--------------------------------------------------------------------------------------------------------------
stepperY.curr[6]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[6]        11.970       -0.861
stepperY.curr[7]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[7]        11.970       -0.861
stepperY.curr[4]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[4]        11.970       -0.733
stepperY.curr[5]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[5]        11.970       -0.733
stepperY.state[0]     Main|osc_clk_inferred_clock     FD1P3AY     D       state_RNO[0]     10.542       -0.717
stepperY.state[1]     Main|osc_clk_inferred_clock     FD1P3AX     D       state_RNO[1]     10.542       -0.717
stepperY.state[2]     Main|osc_clk_inferred_clock     FD1P3AX     D       state_RNO[2]     10.542       -0.717
stepperY.state[3]     Main|osc_clk_inferred_clock     FD1P3AX     D       state_RNO[3]     10.542       -0.717
stepperY.curr[2]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[2]        11.970       -0.605
stepperY.curr[3]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[3]        11.970       -0.605
==============================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      11.545
    - Setup time:                            -0.425
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         11.970

    - Propagation time:                      12.831
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.861

    Number of logic level(s):                11
    Starting point:                          uartRX1.target_pipe_2_fast / Q
    Ending point:                            stepperY.curr[7] / D
    The start point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                               Pin       Pin               Arrival     No. of    
Name                            Type         Name      Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
uartRX1.target_pipe_2_fast      FD1P3AX      Q         Out     1.552     1.552       -         
target_pipe_2_fast              Net          -         -       -         -           3         
uartRX1.targetY_latmux          ORCALUT4     C         In      0.000     1.552       -         
uartRX1.targetY_latmux          ORCALUT4     Z         Out     0.337     1.889       -         
targetY[0]                      Net          -         -       -         -           6         
stepperY.target_2_0_cry_1_0     CCU2         B0        In      0.000     1.889       -         
stepperY.target_2_0_cry_1_0     CCU2         COUT1     Out     1.761     3.650       -         
target_2_0_cry_2                Net          -         -       -         -           1         
stepperY.target_2_0_cry_3_0     CCU2         CIN       In      0.000     3.650       -         
stepperY.target_2_0_cry_3_0     CCU2         S1        Out     1.970     5.620       -         
target[5]                       Net          -         -       -         -           3         
stepperY.state21_cry_4_0        CCU2         B1        In      0.000     5.620       -         
stepperY.state21_cry_4_0        CCU2         COUT1     Out     1.761     7.380       -         
state21_cry_5                   Net          -         -       -         -           1         
stepperY.state21_cry_6_0        CCU2         CIN       In      0.000     7.380       -         
stepperY.state21_cry_6_0        CCU2         COUT1     Out     0.128     7.508       -         
state21_cry_7                   Net          -         -       -         -           1         
stepperY.state21_cry_8_0        CCU2         CIN       In      0.000     7.508       -         
stepperY.state21_cry_8_0        CCU2         COUT1     Out     0.128     7.636       -         
state21_cry_9                   Net          -         -       -         -           1         
stepperY.state21_cry_10_0       CCU2         CIN       In      0.000     7.636       -         
stepperY.state21_cry_10_0       CCU2         COUT0     Out     1.412     9.049       -         
curr_0                          Net          -         -       -         -           15        
stepperY.curr_cry_0[0]          CCU2         A0        In      0.000     9.049       -         
stepperY.curr_cry_0[0]          CCU2         COUT1     Out     1.761     10.810      -         
curr_cry[1]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[2]          CCU2         CIN       In      0.000     10.810      -         
stepperY.curr_cry_0[2]          CCU2         COUT1     Out     0.128     10.938      -         
curr_cry[3]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[4]          CCU2         CIN       In      0.000     10.938      -         
stepperY.curr_cry_0[4]          CCU2         COUT1     Out     0.128     11.066      -         
curr_cry[5]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[6]          CCU2         CIN       In      0.000     11.066      -         
stepperY.curr_cry_0[6]          CCU2         S1        Out     1.766     12.831      -         
curr_s[7]                       Net          -         -       -         -           1         
stepperY.curr[7]                FD1P3AX      D         In      0.000     12.831      -         
===============================================================================================


Path information for path number 2: 
      Requested Period:                      11.545
    - Setup time:                            -0.425
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         11.970

    - Propagation time:                      12.831
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.861

    Number of logic level(s):                11
    Starting point:                          uartRX1.target_pipe_2_fast / Q
    Ending point:                            stepperY.curr[7] / D
    The start point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                               Pin       Pin               Arrival     No. of    
Name                            Type         Name      Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
uartRX1.target_pipe_2_fast      FD1P3AX      Q         Out     1.552     1.552       -         
target_pipe_2_fast              Net          -         -       -         -           3         
uartRX1.targetY_latmux_0        ORCALUT4     C         In      0.000     1.552       -         
uartRX1.targetY_latmux_0        ORCALUT4     Z         Out     0.337     1.889       -         
targetY[1]                      Net          -         -       -         -           5         
stepperY.target_2_0_cry_1_0     CCU2         A0        In      0.000     1.889       -         
stepperY.target_2_0_cry_1_0     CCU2         COUT1     Out     1.761     3.650       -         
target_2_0_cry_2                Net          -         -       -         -           1         
stepperY.target_2_0_cry_3_0     CCU2         CIN       In      0.000     3.650       -         
stepperY.target_2_0_cry_3_0     CCU2         S1        Out     1.970     5.620       -         
target[5]                       Net          -         -       -         -           3         
stepperY.state21_cry_4_0        CCU2         B1        In      0.000     5.620       -         
stepperY.state21_cry_4_0        CCU2         COUT1     Out     1.761     7.380       -         
state21_cry_5                   Net          -         -       -         -           1         
stepperY.state21_cry_6_0        CCU2         CIN       In      0.000     7.380       -         
stepperY.state21_cry_6_0        CCU2         COUT1     Out     0.128     7.508       -         
state21_cry_7                   Net          -         -       -         -           1         
stepperY.state21_cry_8_0        CCU2         CIN       In      0.000     7.508       -         
stepperY.state21_cry_8_0        CCU2         COUT1     Out     0.128     7.636       -         
state21_cry_9                   Net          -         -       -         -           1         
stepperY.state21_cry_10_0       CCU2         CIN       In      0.000     7.636       -         
stepperY.state21_cry_10_0       CCU2         COUT0     Out     1.412     9.049       -         
curr_0                          Net          -         -       -         -           15        
stepperY.curr_cry_0[0]          CCU2         A0        In      0.000     9.049       -         
stepperY.curr_cry_0[0]          CCU2         COUT1     Out     1.761     10.810      -         
curr_cry[1]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[2]          CCU2         CIN       In      0.000     10.810      -         
stepperY.curr_cry_0[2]          CCU2         COUT1     Out     0.128     10.938      -         
curr_cry[3]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[4]          CCU2         CIN       In      0.000     10.938      -         
stepperY.curr_cry_0[4]          CCU2         COUT1     Out     0.128     11.066      -         
curr_cry[5]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[6]          CCU2         CIN       In      0.000     11.066      -         
stepperY.curr_cry_0[6]          CCU2         S1        Out     1.766     12.831      -         
curr_s[7]                       Net          -         -       -         -           1         
stepperY.curr[7]                FD1P3AX      D         In      0.000     12.831      -         
===============================================================================================


Path information for path number 3: 
      Requested Period:                      11.545
    - Setup time:                            -0.425
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         11.970

    - Propagation time:                      12.831
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.861

    Number of logic level(s):                11
    Starting point:                          uartRX1.target_pipe_2_fast / Q
    Ending point:                            stepperY.curr[7] / D
    The start point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                               Pin       Pin               Arrival     No. of    
Name                            Type         Name      Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
uartRX1.target_pipe_2_fast      FD1P3AX      Q         Out     1.552     1.552       -         
target_pipe_2_fast              Net          -         -       -         -           3         
uartRX1.targetY_latmux_1        ORCALUT4     C         In      0.000     1.552       -         
uartRX1.targetY_latmux_1        ORCALUT4     Z         Out     0.337     1.889       -         
targetY[2]                      Net          -         -       -         -           2         
stepperY.target_2_0_cry_1_0     CCU2         A1        In      0.000     1.889       -         
stepperY.target_2_0_cry_1_0     CCU2         COUT1     Out     1.761     3.650       -         
target_2_0_cry_2                Net          -         -       -         -           1         
stepperY.target_2_0_cry_3_0     CCU2         CIN       In      0.000     3.650       -         
stepperY.target_2_0_cry_3_0     CCU2         S1        Out     1.970     5.620       -         
target[5]                       Net          -         -       -         -           3         
stepperY.state21_cry_4_0        CCU2         B1        In      0.000     5.620       -         
stepperY.state21_cry_4_0        CCU2         COUT1     Out     1.761     7.380       -         
state21_cry_5                   Net          -         -       -         -           1         
stepperY.state21_cry_6_0        CCU2         CIN       In      0.000     7.380       -         
stepperY.state21_cry_6_0        CCU2         COUT1     Out     0.128     7.508       -         
state21_cry_7                   Net          -         -       -         -           1         
stepperY.state21_cry_8_0        CCU2         CIN       In      0.000     7.508       -         
stepperY.state21_cry_8_0        CCU2         COUT1     Out     0.128     7.636       -         
state21_cry_9                   Net          -         -       -         -           1         
stepperY.state21_cry_10_0       CCU2         CIN       In      0.000     7.636       -         
stepperY.state21_cry_10_0       CCU2         COUT0     Out     1.412     9.049       -         
curr_0                          Net          -         -       -         -           15        
stepperY.curr_cry_0[0]          CCU2         A0        In      0.000     9.049       -         
stepperY.curr_cry_0[0]          CCU2         COUT1     Out     1.761     10.810      -         
curr_cry[1]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[2]          CCU2         CIN       In      0.000     10.810      -         
stepperY.curr_cry_0[2]          CCU2         COUT1     Out     0.128     10.938      -         
curr_cry[3]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[4]          CCU2         CIN       In      0.000     10.938      -         
stepperY.curr_cry_0[4]          CCU2         COUT1     Out     0.128     11.066      -         
curr_cry[5]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[6]          CCU2         CIN       In      0.000     11.066      -         
stepperY.curr_cry_0[6]          CCU2         S1        Out     1.766     12.831      -         
curr_s[7]                       Net          -         -       -         -           1         
stepperY.curr[7]                FD1P3AX      D         In      0.000     12.831      -         
===============================================================================================


Path information for path number 4: 
      Requested Period:                      11.545
    - Setup time:                            -0.425
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         11.970

    - Propagation time:                      12.831
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.861

    Number of logic level(s):                11
    Starting point:                          uartRX1.target_pipe_2_fast / Q
    Ending point:                            stepperY.curr[7] / D
    The start point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                               Pin       Pin               Arrival     No. of    
Name                            Type         Name      Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
uartRX1.target_pipe_2_fast      FD1P3AX      Q         Out     1.552     1.552       -         
target_pipe_2_fast              Net          -         -       -         -           3         
uartRX1.targetY_latmux          ORCALUT4     C         In      0.000     1.552       -         
uartRX1.targetY_latmux          ORCALUT4     Z         Out     0.337     1.889       -         
targetY[0]                      Net          -         -       -         -           6         
stepperY.target_2_0_cry_1_0     CCU2         B0        In      0.000     1.889       -         
stepperY.target_2_0_cry_1_0     CCU2         COUT1     Out     1.761     3.650       -         
target_2_0_cry_2                Net          -         -       -         -           1         
stepperY.target_2_0_cry_3_0     CCU2         CIN       In      0.000     3.650       -         
stepperY.target_2_0_cry_3_0     CCU2         COUT1     Out     0.128     3.778       -         
target_2_0_cry_4                Net          -         -       -         -           1         
stepperY.target_2_0_cry_5_0     CCU2         CIN       In      0.000     3.778       -         
stepperY.target_2_0_cry_5_0     CCU2         S1        Out     1.970     5.747       -         
target[7]                       Net          -         -       -         -           3         
stepperY.state21_cry_6_0        CCU2         B1        In      0.000     5.747       -         
stepperY.state21_cry_6_0        CCU2         COUT1     Out     1.761     7.508       -         
state21_cry_7                   Net          -         -       -         -           1         
stepperY.state21_cry_8_0        CCU2         CIN       In      0.000     7.508       -         
stepperY.state21_cry_8_0        CCU2         COUT1     Out     0.128     7.636       -         
state21_cry_9                   Net          -         -       -         -           1         
stepperY.state21_cry_10_0       CCU2         CIN       In      0.000     7.636       -         
stepperY.state21_cry_10_0       CCU2         COUT0     Out     1.412     9.049       -         
curr_0                          Net          -         -       -         -           15        
stepperY.curr_cry_0[0]          CCU2         A0        In      0.000     9.049       -         
stepperY.curr_cry_0[0]          CCU2         COUT1     Out     1.761     10.810      -         
curr_cry[1]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[2]          CCU2         CIN       In      0.000     10.810      -         
stepperY.curr_cry_0[2]          CCU2         COUT1     Out     0.128     10.938      -         
curr_cry[3]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[4]          CCU2         CIN       In      0.000     10.938      -         
stepperY.curr_cry_0[4]          CCU2         COUT1     Out     0.128     11.066      -         
curr_cry[5]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[6]          CCU2         CIN       In      0.000     11.066      -         
stepperY.curr_cry_0[6]          CCU2         S1        Out     1.766     12.831      -         
curr_s[7]                       Net          -         -       -         -           1         
stepperY.curr[7]                FD1P3AX      D         In      0.000     12.831      -         
===============================================================================================


Path information for path number 5: 
      Requested Period:                      11.545
    - Setup time:                            -0.425
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         11.970

    - Propagation time:                      12.831
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.861

    Number of logic level(s):                11
    Starting point:                          uartRX1.target_pipe_2_fast / Q
    Ending point:                            stepperY.curr[7] / D
    The start point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                               Pin       Pin               Arrival     No. of    
Name                            Type         Name      Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
uartRX1.target_pipe_2_fast      FD1P3AX      Q         Out     1.552     1.552       -         
target_pipe_2_fast              Net          -         -       -         -           3         
uartRX1.targetY_latmux          ORCALUT4     C         In      0.000     1.552       -         
uartRX1.targetY_latmux          ORCALUT4     Z         Out     0.337     1.889       -         
targetY[0]                      Net          -         -       -         -           6         
stepperY.target_2_0_cry_1_0     CCU2         B0        In      0.000     1.889       -         
stepperY.target_2_0_cry_1_0     CCU2         COUT1     Out     1.761     3.650       -         
target_2_0_cry_2                Net          -         -       -         -           1         
stepperY.target_2_0_cry_3_0     CCU2         CIN       In      0.000     3.650       -         
stepperY.target_2_0_cry_3_0     CCU2         S0        Out     1.970     5.620       -         
target[4]                       Net          -         -       -         -           3         
stepperY.state21_cry_4_0        CCU2         B0        In      0.000     5.620       -         
stepperY.state21_cry_4_0        CCU2         COUT1     Out     1.761     7.380       -         
state21_cry_5                   Net          -         -       -         -           1         
stepperY.state21_cry_6_0        CCU2         CIN       In      0.000     7.380       -         
stepperY.state21_cry_6_0        CCU2         COUT1     Out     0.128     7.508       -         
state21_cry_7                   Net          -         -       -         -           1         
stepperY.state21_cry_8_0        CCU2         CIN       In      0.000     7.508       -         
stepperY.state21_cry_8_0        CCU2         COUT1     Out     0.128     7.636       -         
state21_cry_9                   Net          -         -       -         -           1         
stepperY.state21_cry_10_0       CCU2         CIN       In      0.000     7.636       -         
stepperY.state21_cry_10_0       CCU2         COUT0     Out     1.412     9.049       -         
curr_0                          Net          -         -       -         -           15        
stepperY.curr_cry_0[0]          CCU2         A0        In      0.000     9.049       -         
stepperY.curr_cry_0[0]          CCU2         COUT1     Out     1.761     10.810      -         
curr_cry[1]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[2]          CCU2         CIN       In      0.000     10.810      -         
stepperY.curr_cry_0[2]          CCU2         COUT1     Out     0.128     10.938      -         
curr_cry[3]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[4]          CCU2         CIN       In      0.000     10.938      -         
stepperY.curr_cry_0[4]          CCU2         COUT1     Out     0.128     11.066      -         
curr_cry[5]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[6]          CCU2         CIN       In      0.000     11.066      -         
stepperY.curr_cry_0[6]          CCU2         S1        Out     1.766     12.831      -         
curr_s[7]                       Net          -         -       -         -           1         
stepperY.curr[7]                FD1P3AX      D         In      0.000     12.831      -         
===============================================================================================



##### END OF TIMING REPORT #####]

Constraints that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 144MB peak: 146MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 144MB peak: 146MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2280c-3

Register bits: 164 of 2280 (7%)
PIC Latch:       0
I/O cells:       18


Details:
CCU2:           59
FD1P3AX:        102
FD1P3AY:        2
FD1S3AX:        46
FD1S3IX:        14
GSR:            1
IB:             1
INV:            13
OB:             16
OBZ:            1
ORCALUT4:       115
OSCC:           1
PUR:            1
VHI:            7
VLO:            7
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 54MB peak: 146MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Sat Sep 03 17:32:15 2016

###########################################################]