Synopsys Lattice Technology Mapper, Version maplat, Build 1368R, Built Jan  8 2016 09:37:50
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version K-2015.09L-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N:MO111 : main.v(4) | Tristate driver sgnServo (in view: work.Main(verilog)) on net sgnServo (in view: work.Main(verilog)) has its enable tied to GND.

Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 
@N:FX493 :  | Applying initial value "00000000" on instance stepperY.target[7:0]  
@N:FX493 :  | Applying initial value "0001" on instance stepperY.state[3:0]  
@N:FX493 :  | Applying initial value "00000000" on instance stepperY.target[7:0]  
@N:FX493 :  | Applying initial value "0001" on instance stepperY.state[3:0]  
@N:FX493 :  | Applying initial value "00000000" on instance targetY[7:0]  
@N:FX493 :  | Applying initial value "00000000" on instance targetX[7:0]  

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N: : stepper.v(17) | Found updn counter in view:work.Stepper_1(verilog) inst curr[7:0] 
@N:MF179 : stepper.v(14) | Found 8 bit by 8 bit '==' comparator, 'un1_isBusy'
@N: : stepper.v(17) | Found updn counter in view:work.Stepper_0(verilog) inst curr[7:0] 
@N:MF179 : stepper.v(14) | Found 8 bit by 8 bit '==' comparator, 'un1_isBusy'

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)

@N:FA113 : timerx.v(9) | Pipelining module c_delay_1[9:0]
@N:MF169 : timerx.v(7) | Register c_delay[9:0] pushed in.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 141MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 141MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 141MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 142MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -2.70ns		 141 /       123
   2		0h:00m:01s		    -2.70ns		 139 /       123
   3		0h:00m:01s		    -2.68ns		 138 /       123
@N:FX271 : uartrx.v(13) | Instance "uartRX1.state_0[0]" with 6 loads replicated 1 times to improve timing 
@N:FX271 : uartrx.v(13) | Instance "uartRX1.state[1]" with 5 loads replicated 1 times to improve timing 
@N:FX271 : uartrx.v(13) | Instance "uartRX1.index[1]" with 12 loads replicated 1 times to improve timing 
@N:FX271 : uartrx.v(13) | Instance "uartRX1.index[2]" with 11 loads replicated 1 times to improve timing 
@N:FX271 : uartrx.v(13) | Instance "uartRX1.index[0]" with 9 loads replicated 1 times to improve timing 
Timing driven replication report
Added 5 Registers via timing driven replication
Added 5 LUTs via timing driven replication

   4		0h:00m:02s		    -2.52ns		 173 /       128
   5		0h:00m:02s		    -2.12ns		 174 /       128
   6		0h:00m:02s		    -2.05ns		 175 /       128
   7		0h:00m:02s		    -2.00ns		 175 /       128
@N:FX271 :  | Instance "uartRX1.timeRX1.c_delay_pipe_7" with 19 loads replicated 1 times to improve timing  
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication


   8		0h:00m:02s		    -2.52ns		 175 /       129
   9		0h:00m:02s		    -2.52ns		 175 /       129
  10		0h:00m:02s		    -2.52ns		 175 /       129

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 142MB)

@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
@N:MO111 : main.v(4) | Tristate driver sgnServo_obuft.un1[0] (in view: work.Main(verilog)) on net sgnServo (in view: work.Main(verilog)) has its enable tied to GND.

Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 142MB)

@N:MT611 :  | Automatically generated clock StepperTime_0|tmr_derived_clock is not used and is being removed 
@N:MT611 :  | Automatically generated clock StepperTime_1|tmr_derived_clock is not used and is being removed 
@N:MT611 :  | Automatically generated clock TimeRX|tmrRX_derived_clock is not used and is being removed 
@N:MT611 :  | Automatically generated clock UartRX|isBusy_derived_clock is not used and is being removed 
@N:MT611 :  | Automatically generated clock Main|count_derived_clock[0] is not used and is being removed 


@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 145 clock pin(s) of sequential element(s)
0 instances converted, 145 sequential instances remain driven by gated/generated clocks

================================================================================================= Gated/Generated Clocks =================================================================================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance     Explanation                                                                                                                   
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        OSCC_1              OSCC                   145        count[0]            Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
==========================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 109MB peak: 143MB)

Writing Analyst data base C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\synwork\PlotterV3_Imp_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 140MB peak: 143MB)

Writing EDIF Netlist and constraint files
@N:FX1056 :  | Writing EDF file: C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\PlotterV3_Imp.edi 
K-2015.09L-2
@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 144MB peak: 146MB)


Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 143MB peak: 146MB)

@W:MT420 :  | Found inferred clock Main|osc_clk_inferred_clock with period 7.11ns. Please declare a user-defined clock on object "n:osc_clk" 


##### START OF TIMING REPORT #####[
# Timing Report written on Sat Sep 03 16:39:22 2016
#


Top view:               Main
Requested Frequency:    140.7 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 



Performance Summary
*******************


Worst slack in design: -1.254

                                Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock                  Frequency     Frequency     Period        Period        Slack      Type         Group                
-------------------------------------------------------------------------------------------------------------------------------------
Main|osc_clk_inferred_clock     140.7 MHz     119.6 MHz     7.108         8.363         -1.254     inferred     Autoconstr_clkgroup_0
=====================================================================================================================================





Clock Relationships
*******************

Clocks                                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting                     Ending                       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------------
Main|osc_clk_inferred_clock  Main|osc_clk_inferred_clock  |  7.108       -1.254  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: Main|osc_clk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                       Starting                                                          Arrival           
Instance               Reference                       Type        Pin     Net           Time        Slack 
                       Clock                                                                               
-----------------------------------------------------------------------------------------------------------
stepperX.curr[0]       Main|osc_clk_inferred_clock     FD1P3AX     Q       curr[0]       1.612       -1.254
stepperY.curr[0]       Main|osc_clk_inferred_clock     FD1P3AX     Q       curr[0]       1.612       -1.254
stepperX.curr[1]       Main|osc_clk_inferred_clock     FD1P3AX     Q       curr[1]       1.612       -1.254
stepperY.curr[1]       Main|osc_clk_inferred_clock     FD1P3AX     Q       curr[1]       1.612       -1.254
stepperY.target[0]     Main|osc_clk_inferred_clock     FD1P3AX     Q       state22_0     1.552       -1.194
stepperX.target[0]     Main|osc_clk_inferred_clock     FD1P3AX     Q       state22_0     1.552       -1.194
stepperX.target[1]     Main|osc_clk_inferred_clock     FD1P3AX     Q       state22_1     1.552       -1.194
stepperY.target[1]     Main|osc_clk_inferred_clock     FD1P3AX     Q       state22_1     1.552       -1.194
stepperX.curr[2]       Main|osc_clk_inferred_clock     FD1P3AX     Q       curr[2]       1.612       -1.126
stepperY.curr[2]       Main|osc_clk_inferred_clock     FD1P3AX     Q       curr[2]       1.612       -1.126
===========================================================================================================


Ending Points with Worst Slack
******************************

                      Starting                                                             Required           
Instance              Reference                       Type        Pin     Net              Time         Slack 
                      Clock                                                                                   
--------------------------------------------------------------------------------------------------------------
stepperY.curr[6]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[6]        7.533        -1.254
stepperX.curr[6]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[6]        7.533        -1.254
stepperY.curr[7]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[7]        7.533        -1.254
stepperX.curr[7]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[7]        7.533        -1.254
stepperY.curr[4]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[4]        7.533        -1.126
stepperX.curr[4]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[4]        7.533        -1.126
stepperX.curr[5]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[5]        7.533        -1.126
stepperY.curr[5]      Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[5]        7.533        -1.126
stepperX.state[0]     Main|osc_clk_inferred_clock     FD1P3AY     D       state_1[0]       6.105        -1.110
stepperY.state[0]     Main|osc_clk_inferred_clock     FD1P3AY     D       state_1_0[0]     6.105        -1.110
==============================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      7.108
    - Setup time:                            -0.425
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.533

    - Propagation time:                      8.787
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.254

    Number of logic level(s):                8
    Starting point:                          stepperX.curr[0] / Q
    Ending point:                            stepperX.curr[7] / D
    The start point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                           Pin       Pin               Arrival     No. of    
Name                         Type        Name      Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
stepperX.curr[0]             FD1P3AX     Q         Out     1.612     1.612       -         
curr[0]                      Net         -         -       -         -           4         
stepperX.state21_cry_0_0     CCU2        A0        In      0.000     1.612       -         
stepperX.state21_cry_0_0     CCU2        COUT1     Out     1.761     3.373       -         
state21_cry_1                Net         -         -       -         -           1         
stepperX.state21_cry_2_0     CCU2        CIN       In      0.000     3.373       -         
stepperX.state21_cry_2_0     CCU2        COUT1     Out     0.128     3.501       -         
state21_cry_3                Net         -         -       -         -           1         
stepperX.state21_cry_4_0     CCU2        CIN       In      0.000     3.501       -         
stepperX.state21_cry_4_0     CCU2        COUT1     Out     0.128     3.629       -         
state21_cry_5                Net         -         -       -         -           1         
stepperX.state21_cry_6_0     CCU2        CIN       In      0.000     3.629       -         
stepperX.state21_cry_6_0     CCU2        COUT1     Out     1.376     5.005       -         
curr_0                       Net         -         -       -         -           11        
stepperX.curr_cry_0[0]       CCU2        A0        In      0.000     5.005       -         
stepperX.curr_cry_0[0]       CCU2        COUT1     Out     1.761     6.766       -         
curr_cry[1]                  Net         -         -       -         -           1         
stepperX.curr_cry_0[2]       CCU2        CIN       In      0.000     6.766       -         
stepperX.curr_cry_0[2]       CCU2        COUT1     Out     0.128     6.894       -         
curr_cry[3]                  Net         -         -       -         -           1         
stepperX.curr_cry_0[4]       CCU2        CIN       In      0.000     6.894       -         
stepperX.curr_cry_0[4]       CCU2        COUT1     Out     0.128     7.022       -         
curr_cry[5]                  Net         -         -       -         -           1         
stepperX.curr_cry_0[6]       CCU2        CIN       In      0.000     7.022       -         
stepperX.curr_cry_0[6]       CCU2        S1        Out     1.766     8.787       -         
curr_s[7]                    Net         -         -       -         -           1         
stepperX.curr[7]             FD1P3AX     D         In      0.000     8.787       -         
===========================================================================================


Path information for path number 2: 
      Requested Period:                      7.108
    - Setup time:                            -0.425
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.533

    - Propagation time:                      8.787
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.254

    Number of logic level(s):                8
    Starting point:                          stepperY.curr[0] / Q
    Ending point:                            stepperY.curr[7] / D
    The start point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                           Pin       Pin               Arrival     No. of    
Name                         Type        Name      Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
stepperY.curr[0]             FD1P3AX     Q         Out     1.612     1.612       -         
curr[0]                      Net         -         -       -         -           4         
stepperY.state21_cry_0_0     CCU2        A0        In      0.000     1.612       -         
stepperY.state21_cry_0_0     CCU2        COUT1     Out     1.761     3.373       -         
state21_cry_1                Net         -         -       -         -           1         
stepperY.state21_cry_2_0     CCU2        CIN       In      0.000     3.373       -         
stepperY.state21_cry_2_0     CCU2        COUT1     Out     0.128     3.501       -         
state21_cry_3                Net         -         -       -         -           1         
stepperY.state21_cry_4_0     CCU2        CIN       In      0.000     3.501       -         
stepperY.state21_cry_4_0     CCU2        COUT1     Out     0.128     3.629       -         
state21_cry_5                Net         -         -       -         -           1         
stepperY.state21_cry_6_0     CCU2        CIN       In      0.000     3.629       -         
stepperY.state21_cry_6_0     CCU2        COUT1     Out     1.376     5.005       -         
curr_0                       Net         -         -       -         -           11        
stepperY.curr_cry_0[0]       CCU2        A0        In      0.000     5.005       -         
stepperY.curr_cry_0[0]       CCU2        COUT1     Out     1.761     6.766       -         
curr_cry[1]                  Net         -         -       -         -           1         
stepperY.curr_cry_0[2]       CCU2        CIN       In      0.000     6.766       -         
stepperY.curr_cry_0[2]       CCU2        COUT1     Out     0.128     6.894       -         
curr_cry[3]                  Net         -         -       -         -           1         
stepperY.curr_cry_0[4]       CCU2        CIN       In      0.000     6.894       -         
stepperY.curr_cry_0[4]       CCU2        COUT1     Out     0.128     7.022       -         
curr_cry[5]                  Net         -         -       -         -           1         
stepperY.curr_cry_0[6]       CCU2        CIN       In      0.000     7.022       -         
stepperY.curr_cry_0[6]       CCU2        S1        Out     1.766     8.787       -         
curr_s[7]                    Net         -         -       -         -           1         
stepperY.curr[7]             FD1P3AX     D         In      0.000     8.787       -         
===========================================================================================


Path information for path number 3: 
      Requested Period:                      7.108
    - Setup time:                            -0.425
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.533

    - Propagation time:                      8.787
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.254

    Number of logic level(s):                8
    Starting point:                          stepperX.curr[1] / Q
    Ending point:                            stepperX.curr[7] / D
    The start point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                           Pin       Pin               Arrival     No. of    
Name                         Type        Name      Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
stepperX.curr[1]             FD1P3AX     Q         Out     1.612     1.612       -         
curr[1]                      Net         -         -       -         -           4         
stepperX.state21_cry_0_0     CCU2        A1        In      0.000     1.612       -         
stepperX.state21_cry_0_0     CCU2        COUT1     Out     1.761     3.373       -         
state21_cry_1                Net         -         -       -         -           1         
stepperX.state21_cry_2_0     CCU2        CIN       In      0.000     3.373       -         
stepperX.state21_cry_2_0     CCU2        COUT1     Out     0.128     3.501       -         
state21_cry_3                Net         -         -       -         -           1         
stepperX.state21_cry_4_0     CCU2        CIN       In      0.000     3.501       -         
stepperX.state21_cry_4_0     CCU2        COUT1     Out     0.128     3.629       -         
state21_cry_5                Net         -         -       -         -           1         
stepperX.state21_cry_6_0     CCU2        CIN       In      0.000     3.629       -         
stepperX.state21_cry_6_0     CCU2        COUT1     Out     1.376     5.005       -         
curr_0                       Net         -         -       -         -           11        
stepperX.curr_cry_0[0]       CCU2        A0        In      0.000     5.005       -         
stepperX.curr_cry_0[0]       CCU2        COUT1     Out     1.761     6.766       -         
curr_cry[1]                  Net         -         -       -         -           1         
stepperX.curr_cry_0[2]       CCU2        CIN       In      0.000     6.766       -         
stepperX.curr_cry_0[2]       CCU2        COUT1     Out     0.128     6.894       -         
curr_cry[3]                  Net         -         -       -         -           1         
stepperX.curr_cry_0[4]       CCU2        CIN       In      0.000     6.894       -         
stepperX.curr_cry_0[4]       CCU2        COUT1     Out     0.128     7.022       -         
curr_cry[5]                  Net         -         -       -         -           1         
stepperX.curr_cry_0[6]       CCU2        CIN       In      0.000     7.022       -         
stepperX.curr_cry_0[6]       CCU2        S1        Out     1.766     8.787       -         
curr_s[7]                    Net         -         -       -         -           1         
stepperX.curr[7]             FD1P3AX     D         In      0.000     8.787       -         
===========================================================================================


Path information for path number 4: 
      Requested Period:                      7.108
    - Setup time:                            -0.425
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.533

    - Propagation time:                      8.787
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.254

    Number of logic level(s):                8
    Starting point:                          stepperY.curr[1] / Q
    Ending point:                            stepperY.curr[7] / D
    The start point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                           Pin       Pin               Arrival     No. of    
Name                         Type        Name      Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
stepperY.curr[1]             FD1P3AX     Q         Out     1.612     1.612       -         
curr[1]                      Net         -         -       -         -           4         
stepperY.state21_cry_0_0     CCU2        A1        In      0.000     1.612       -         
stepperY.state21_cry_0_0     CCU2        COUT1     Out     1.761     3.373       -         
state21_cry_1                Net         -         -       -         -           1         
stepperY.state21_cry_2_0     CCU2        CIN       In      0.000     3.373       -         
stepperY.state21_cry_2_0     CCU2        COUT1     Out     0.128     3.501       -         
state21_cry_3                Net         -         -       -         -           1         
stepperY.state21_cry_4_0     CCU2        CIN       In      0.000     3.501       -         
stepperY.state21_cry_4_0     CCU2        COUT1     Out     0.128     3.629       -         
state21_cry_5                Net         -         -       -         -           1         
stepperY.state21_cry_6_0     CCU2        CIN       In      0.000     3.629       -         
stepperY.state21_cry_6_0     CCU2        COUT1     Out     1.376     5.005       -         
curr_0                       Net         -         -       -         -           11        
stepperY.curr_cry_0[0]       CCU2        A0        In      0.000     5.005       -         
stepperY.curr_cry_0[0]       CCU2        COUT1     Out     1.761     6.766       -         
curr_cry[1]                  Net         -         -       -         -           1         
stepperY.curr_cry_0[2]       CCU2        CIN       In      0.000     6.766       -         
stepperY.curr_cry_0[2]       CCU2        COUT1     Out     0.128     6.894       -         
curr_cry[3]                  Net         -         -       -         -           1         
stepperY.curr_cry_0[4]       CCU2        CIN       In      0.000     6.894       -         
stepperY.curr_cry_0[4]       CCU2        COUT1     Out     0.128     7.022       -         
curr_cry[5]                  Net         -         -       -         -           1         
stepperY.curr_cry_0[6]       CCU2        CIN       In      0.000     7.022       -         
stepperY.curr_cry_0[6]       CCU2        S1        Out     1.766     8.787       -         
curr_s[7]                    Net         -         -       -         -           1         
stepperY.curr[7]             FD1P3AX     D         In      0.000     8.787       -         
===========================================================================================


Path information for path number 5: 
      Requested Period:                      7.108
    - Setup time:                            -0.425
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         7.533

    - Propagation time:                      8.787
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.254

    Number of logic level(s):                8
    Starting point:                          stepperX.curr[0] / Q
    Ending point:                            stepperX.curr[7] / D
    The start point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                           Pin       Pin               Arrival     No. of    
Name                         Type        Name      Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
stepperX.curr[0]             FD1P3AX     Q         Out     1.612     1.612       -         
curr[0]                      Net         -         -       -         -           4         
stepperX.state21_cry_0_0     CCU2        A0        In      0.000     1.612       -         
stepperX.state21_cry_0_0     CCU2        COUT1     Out     1.761     3.373       -         
state21_cry_1                Net         -         -       -         -           1         
stepperX.state21_cry_2_0     CCU2        CIN       In      0.000     3.373       -         
stepperX.state21_cry_2_0     CCU2        COUT1     Out     0.128     3.501       -         
state21_cry_3                Net         -         -       -         -           1         
stepperX.state21_cry_4_0     CCU2        CIN       In      0.000     3.501       -         
stepperX.state21_cry_4_0     CCU2        COUT1     Out     0.128     3.629       -         
state21_cry_5                Net         -         -       -         -           1         
stepperX.state21_cry_6_0     CCU2        CIN       In      0.000     3.629       -         
stepperX.state21_cry_6_0     CCU2        COUT1     Out     1.376     5.005       -         
curr_0                       Net         -         -       -         -           11        
stepperX.curr_cry_0[0]       CCU2        A1        In      0.000     5.005       -         
stepperX.curr_cry_0[0]       CCU2        COUT1     Out     1.761     6.766       -         
curr_cry[1]                  Net         -         -       -         -           1         
stepperX.curr_cry_0[2]       CCU2        CIN       In      0.000     6.766       -         
stepperX.curr_cry_0[2]       CCU2        COUT1     Out     0.128     6.894       -         
curr_cry[3]                  Net         -         -       -         -           1         
stepperX.curr_cry_0[4]       CCU2        CIN       In      0.000     6.894       -         
stepperX.curr_cry_0[4]       CCU2        COUT1     Out     0.128     7.022       -         
curr_cry[5]                  Net         -         -       -         -           1         
stepperX.curr_cry_0[6]       CCU2        CIN       In      0.000     7.022       -         
stepperX.curr_cry_0[6]       CCU2        S1        Out     1.766     8.787       -         
curr_s[7]                    Net         -         -       -         -           1         
stepperX.curr[7]             FD1P3AX     D         In      0.000     8.787       -         
===========================================================================================



##### END OF TIMING REPORT #####]

Constraints that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 144MB peak: 146MB)


Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 144MB peak: 146MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2280c-3

Register bits: 145 of 2280 (6%)
PIC Latch:       0
I/O cells:       18


Details:
CCU2:           53
FD1P3AX:        72
FD1P3AY:        2
FD1S3AX:        55
FD1S3IX:        16
GSR:            1
IB:             1
INV:            13
OB:             16
OBZ:            1
ORCALUT4:       161
OSCC:           1
PFUMX:          1
PUR:            1
VHI:            7
VLO:            7
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 54MB peak: 146MB)

Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Sat Sep 03 16:39:22 2016

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