@W:FX474 : | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @W:MT529 : timerx.v(7) | Found inferred clock Main|osc_clk_inferred_clock which controls 57 sequential elements including uartRX1.timeRX1.c_delay[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.