Setting log file to 'C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/PlotterV3_Imp/hdla_gen_hierarchy.html'. Starting: parse design source files (VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v (VERI-1482) Analyzing Verilog file C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/Main.v (VERI-1482) Analyzing Verilog file C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/timeRX.v (VERI-1482) Analyzing Verilog file C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/timeTX.v (VERI-1482) Analyzing Verilog file C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/uartRX.v (VERI-1482) Analyzing Verilog file C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/uartTX.v (VERI-1482) Analyzing Verilog file C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/Stepper.v (VERI-1482) Analyzing Verilog file C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/PWM.v (VERI-1482) Analyzing Verilog file C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/StepperTime.v (VERI-1482) Analyzing Verilog file C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/Mikrosecond.v INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/Main.v(1,8-1,12) (VERI-1018) compiling module Main INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/Main.v(1,1-53,10) (VERI-9000) elaborating module 'Main' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v(1372,1-1374,10) (VERI-9000) elaborating module 'OSCC_uniq_1' INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/uartRX.v(1,1-43,10) (VERI-9000) elaborating module 'UartRX_uniq_1' INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/Stepper.v(1,1-51,10) (VERI-9000) elaborating module 'Stepper_uniq_1' INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/Stepper.v(1,1-51,10) (VERI-9000) elaborating module 'Stepper_uniq_2' INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/timeRX.v(1,1-18,10) (VERI-9000) elaborating module 'TimeRX_uniq_1' INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/StepperTime.v(1,1-18,10) (VERI-9000) elaborating module 'StepperTime_uniq_1' INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/StepperTime.v(1,1-18,10) (VERI-9000) elaborating module 'StepperTime_uniq_2' INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/uartTX.v(1,8-1,14) (VERI-1018) compiling module UartTX INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/uartTX.v(1,1-41,10) (VERI-9000) elaborating module 'UartTX' INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/timeTX.v(1,1-18,10) (VERI-9000) elaborating module 'TimeTX_uniq_1' INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/PWM.v(1,8-1,11) (VERI-1018) compiling module PWM INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/PWM.v(1,1-21,10) (VERI-9000) elaborating module 'PWM' INFO - C:/Users/Zabrsa/Dropbox/FPGA/PlotterV3/Mikrosecond.v(1,1-18,10) (VERI-9000) elaborating module 'Mikrosecond_uniq_1' Done: design load finished with (0) errors, and (0) warnings