Synthesis Report
#Build: Synplify Pro K-2015.09L-2, Build 126R, Dec 14 2015
#install: C:\lscc\diamond\3.7_x64\synpbase
#OS: Windows 8 6.2
#Hostname: NTB-ZABRSA

# Sun Sep 04 16:50:20 2016

#Implementation: PlotterV3_Imp

Synopsys HDL Compiler, version comp201509p1, Build 145R, built Dec  9 2015
@N|Running in 64-bit mode
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

Synopsys Verilog Compiler, version comp201509p1, Build 145R, built Dec  9 2015
@N|Running in 64-bit mode
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@I::"C:\lscc\diamond\3.7_x64\synpbase\lib\lucent\machxo.v"
@I::"C:\lscc\diamond\3.7_x64\synpbase\lib\lucent\pmi_def.v"
@I::"C:\lscc\diamond\3.7_x64\synpbase\lib\vlog\hypermods.v"
@I::"C:\lscc\diamond\3.7_x64\synpbase\lib\vlog\umr_capim.v"
@I::"C:\lscc\diamond\3.7_x64\synpbase\lib\vlog\scemi_objects.v"
@I::"C:\lscc\diamond\3.7_x64\synpbase\lib\vlog\scemi_pipes.svh"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Main.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\timeRX.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\timeTX.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\uartRX.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\uartTX.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Stepper.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PWM.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\StepperTime.v"
@I::"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Mikrosecond.v"
Verilog syntax check successful!
File C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Main.v changed - recompiling
Selecting top level module Main
@N: CG364 :"C:\lscc\diamond\3.7_x64\synpbase\lib\lucent\machxo.v":1372:7:1372:10|Synthesizing module OSCC.

@N: CG364 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\timeRX.v":1:7:1:12|Synthesizing module TimeRX.

@N: CL189 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\timeRX.v":7:1:7:6|Register bit c_delay[13] is always 0.
@N: CL189 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\timeRX.v":7:1:7:6|Register bit c_delay[12] is always 0.
@N: CL189 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\timeRX.v":7:1:7:6|Register bit c_delay[11] is always 0.
@N: CL189 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\timeRX.v":7:1:7:6|Register bit c_delay[10] is always 0.
@W: CL279 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\timeRX.v":7:1:7:6|Pruning register bits 13 to 10 of c_delay[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N: CG364 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\uartRX.v":1:7:1:12|Synthesizing module UartRX.

@N: CL189 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\uartRX.v":13:1:13:6|Register bit index[4] is always 0.
@N: CL189 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\uartRX.v":13:1:13:6|Register bit index[5] is always 0.
@N: CL189 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\uartRX.v":13:1:13:6|Register bit index[6] is always 0.
@N: CL189 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\uartRX.v":13:1:13:6|Register bit index[7] is always 0.
@W: CL279 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\uartRX.v":13:1:13:6|Pruning register bits 7 to 4 of index[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N: CG364 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\StepperTime.v":1:7:1:17|Synthesizing module StepperTime.

@N: CG364 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Stepper.v":1:7:1:13|Synthesizing module Stepper.

@N: CG364 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Main.v":1:7:1:10|Synthesizing module Main.

@W: CG360 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Main.v":4:8:4:15|Removing wire sgnServo, as there is no assignment to it.
@W: CL118 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Main.v":40:2:40:3|Latch generated from always block for signal targetY[7:0]; possible missing assignment in an if or case statement.
@W: CL118 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Main.v":40:2:40:3|Latch generated from always block for signal targetX[7:0]; possible missing assignment in an if or case statement.
@W: CL157 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Main.v":4:8:4:15|*Output sgnServo has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Main.v":7:13:7:15|*Output LED has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@N: CL159 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\Main.v":3:7:3:14|Input btnReset is unused.
@N: CL189 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\StepperTime.v":7:1:7:6|Register bit c_delay[19] is always 0.
@N: CL189 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\StepperTime.v":7:1:7:6|Register bit c_delay[20] is always 0.
@N: CL189 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\StepperTime.v":7:1:7:6|Register bit c_delay[21] is always 0.
@N: CL189 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\StepperTime.v":7:1:7:6|Register bit c_delay[22] is always 0.
@W: CL279 :"C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\StepperTime.v":7:1:7:6|Pruning register bits 22 to 19 of c_delay[22:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 74MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sun Sep 04 16:50:20 2016

###########################################################]
Synopsys Netlist Linker, version comp201509p1, Build 145R, built Dec  9 2015
@N|Running in 64-bit mode
File C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sun Sep 04 16:50:21 2016

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sun Sep 04 16:50:21 2016

###########################################################]
Synopsys Netlist Linker, version comp201509p1, Build 145R, built Dec  9 2015
@N|Running in 64-bit mode
File C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\synwork\PlotterV3_Proj_PlotterV3_Imp_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sun Sep 04 16:50:22 2016

###########################################################]
Pre-mapping Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1368R, Built Jan  8 2016 09:37:50
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version K-2015.09L-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@L: C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\PlotterV3_Proj_PlotterV3_Imp_scck.rpt 
Printing clock  summary report in "C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\PlotterV3_Proj_PlotterV3_Imp_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)

@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=3  set on top level netlist Main

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)



Clock Summary
*****************

Start                               Requested     Requested     Clock                                          Clock              
Clock                               Frequency     Period        Type                                           Group              
----------------------------------------------------------------------------------------------------------------------------------
Main|LED_derived_clock[1]           1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Inferred_clkgroup_0
Main|osc_clk_inferred_clock         1.0 MHz       1000.000      inferred                                       Inferred_clkgroup_0
StepperTime_0|tmr_derived_clock     1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Inferred_clkgroup_0
StepperTime_1|tmr_derived_clock     1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Inferred_clkgroup_0
TimeRX|tmrRX_derived_clock          1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Inferred_clkgroup_0
UartRX|isBusy_derived_clock         1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Inferred_clkgroup_0
==================================================================================================================================

@W: MT529 :"c:\users\zabrsa\dropbox\fpga\plotterv3\timerx.v":7:1:7:6|Found inferred clock Main|osc_clk_inferred_clock which controls 51 sequential elements including uartRX1.timeRX1.c_delay[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":7:13:7:15|Tristate driver LED_1 (in view: work.Main(verilog)) on net LED[6] (in view: work.Main(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":7:13:7:15|Tristate driver LED_2 (in view: work.Main(verilog)) on net LED[5] (in view: work.Main(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":7:13:7:15|Tristate driver LED_3 (in view: work.Main(verilog)) on net LED[4] (in view: work.Main(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":7:13:7:15|Tristate driver LED_4 (in view: work.Main(verilog)) on net LED[2] (in view: work.Main(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":4:8:4:15|Tristate driver sgnServo (in view: work.Main(verilog)) on net sgnServo (in view: work.Main(verilog)) has its enable tied to GND.

Available hyper_sources - for debug and ip models
	None Found

None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 140MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Sep 04 16:50:23 2016

###########################################################]
Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 1368R, Built Jan  8 2016 09:37:50
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version K-2015.09L-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)

@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":7:13:7:15|Tristate driver LED_1 (in view: work.Main(verilog)) on net LED[6] (in view: work.Main(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":7:13:7:15|Tristate driver LED_2 (in view: work.Main(verilog)) on net LED[5] (in view: work.Main(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":7:13:7:15|Tristate driver LED_3 (in view: work.Main(verilog)) on net LED[4] (in view: work.Main(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":7:13:7:15|Tristate driver LED_4 (in view: work.Main(verilog)) on net LED[2] (in view: work.Main(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":4:8:4:15|Tristate driver sgnServo (in view: work.Main(verilog)) on net sgnServo (in view: work.Main(verilog)) has its enable tied to GND.

Available hyper_sources - for debug and ip models
	None Found

@N: FX493 |Applying initial value "0001" on instance stepperY.state[3:0] 
@N: FX493 |Applying initial value "0001" on instance stepperY.state[3:0] 
@N: FX493 |Applying initial value "00000000" on instance targetY[7:0] 
@N: FX493 |Applying initial value "00000000" on instance targetX[7:0] 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N:"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Found updn counter in view:work.Stepper_1(verilog) inst curr[15:0] 
@W: MO129 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Sequential instance stepperX.target[10] reduced to a combinational gate by constant propagation
@W: MO129 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Sequential instance stepperX.target[11] reduced to a combinational gate by constant propagation
@W: MO129 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Sequential instance stepperX.target[12] reduced to a combinational gate by constant propagation
@W: MO129 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Sequential instance stepperX.target[13] reduced to a combinational gate by constant propagation
@W: MO129 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Sequential instance stepperX.target[14] reduced to a combinational gate by constant propagation
@W: MO129 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Sequential instance stepperX.target[15] reduced to a combinational gate by constant propagation
@N: MF179 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":14:18:14:32|Found 16 bit by 16 bit '==' comparator, 'un1_isBusy'
@N:"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Found updn counter in view:work.Stepper_0(verilog) inst curr[15:0] 
@W: MO129 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Sequential instance stepperY.target[10] reduced to a combinational gate by constant propagation
@W: MO129 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Sequential instance stepperY.target[11] reduced to a combinational gate by constant propagation
@W: MO129 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Sequential instance stepperY.target[12] reduced to a combinational gate by constant propagation
@W: MO129 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Sequential instance stepperY.target[13] reduced to a combinational gate by constant propagation
@W: MO129 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Sequential instance stepperY.target[14] reduced to a combinational gate by constant propagation
@W: MO129 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Sequential instance stepperY.target[15] reduced to a combinational gate by constant propagation
@N: MF179 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":14:18:14:32|Found 16 bit by 16 bit '==' comparator, 'un1_isBusy'

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)

@N: FA113 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":46:11:46:26|Pipelining module target_2[15:0]
@N: MF169 :"c:\users\zabrsa\dropbox\fpga\plotterv3\stepper.v":17:1:17:6|Register target[15:0] pushed in.
@N: MF169 :"c:\users\zabrsa\dropbox\fpga\plotterv3\uartrx.v":13:1:13:6|Register data[7:0] pushed in.
@N: MF169 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":40:2:40:3|Register targetX[7:0] pushed in.
@N: MF169 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":33:1:33:6|Register count[0] pushed in.
@N: MF169 :"c:\users\zabrsa\dropbox\fpga\plotterv3\uartrx.v":13:1:13:6|Register buffer[7:0] pushed in.
@N: MF169 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":40:2:40:3|Register targetY[7:0] pushed in.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 141MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 141MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		   986.16ns		 119 /       181

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 141MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":4:8:4:15|Tristate driver sgnServo_obuft.un1[0] (in view: work.Main(verilog)) on net sgnServo (in view: work.Main(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":7:13:7:15|Tristate driver LED_obuft_2_.un1[0] (in view: work.Main(verilog)) on net LED[2] (in view: work.Main(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":7:13:7:15|Tristate driver LED_obuft_4_.un1[0] (in view: work.Main(verilog)) on net LED[4] (in view: work.Main(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":7:13:7:15|Tristate driver LED_obuft_5_.un1[0] (in view: work.Main(verilog)) on net LED[5] (in view: work.Main(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\zabrsa\dropbox\fpga\plotterv3\main.v":7:13:7:15|Tristate driver LED_obuft_6_.un1[0] (in view: work.Main(verilog)) on net LED[6] (in view: work.Main(verilog)) has its enable tied to GND.

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 141MB)

@N: MT611 :|Automatically generated clock StepperTime_0|tmr_derived_clock is not used and is being removed
@N: MT611 :|Automatically generated clock StepperTime_1|tmr_derived_clock is not used and is being removed
@N: MT611 :|Automatically generated clock TimeRX|tmrRX_derived_clock is not used and is being removed
@N: MT611 :|Automatically generated clock UartRX|isBusy_derived_clock is not used and is being removed
@N: MT611 :|Automatically generated clock Main|LED_derived_clock[1] is not used and is being removed


@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 181 clock pin(s) of sequential element(s)
0 instances converted, 181 sequential instances remain driven by gated/generated clocks

================================================================================================= Gated/Generated Clocks =================================================================================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance     Explanation                                                                                                                   
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0001       OSCC_1              OSCC                   181        count[0]            Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
==========================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 108MB peak: 142MB)

Writing Analyst data base C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\synwork\PlotterV3_Proj_PlotterV3_Imp_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 140MB peak: 142MB)

Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\PlotterV3_Proj_PlotterV3_Imp.edi
K-2015.09L-2
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 144MB peak: 145MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 143MB peak: 145MB)

@W: MT420 |Found inferred clock Main|osc_clk_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:osc_clk"


##### START OF TIMING REPORT #####[
# Timing Report written on Sun Sep 04 16:50:27 2016
#


Top view:               Main
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary
*******************


Worst slack in design: 986.482

                                Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock                  Frequency     Frequency     Period        Period        Slack       Type         Group              
------------------------------------------------------------------------------------------------------------------------------------
Main|osc_clk_inferred_clock     1.0 MHz       74.0 MHz      1000.000      13.518        986.482     inferred     Inferred_clkgroup_0
====================================================================================================================================





Clock Relationships
*******************

Clocks                                                    |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------------------------------------
Starting                     Ending                       |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------------------------------------
Main|osc_clk_inferred_clock  Main|osc_clk_inferred_clock  |  1000.000    986.482  |  No paths    -      |  No paths    -      |  No paths    -    
==================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: Main|osc_clk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                             Starting                                                                Arrival            
Instance                     Reference                       Type        Pin     Net                 Time        Slack  
                             Clock                                                                                      
------------------------------------------------------------------------------------------------------------------------
stepperY.target_pipe_1_2     Main|osc_clk_inferred_clock     FD1P3AX     Q       LED_cf_7[1]         1.720       986.482
stepperX.target_pipe_9       Main|osc_clk_inferred_clock     FD1P3AX     Q       LED_cf[1]           1.720       986.482
stepperY.target_pipe_0       Main|osc_clk_inferred_clock     FD1P3AX     Q       target_pipe_0       1.348       986.854
stepperX.target_pipe_0       Main|osc_clk_inferred_clock     FD1P3AX     Q       dataRXf[0]          1.348       986.854
stepperY.target_pipe_1_0     Main|osc_clk_inferred_clock     FD1P3AX     Q       target_pipe_1_0     1.348       986.854
stepperX.target_pipe_1_0     Main|osc_clk_inferred_clock     FD1P3AX     Q       dataRXf[1]          1.348       986.854
stepperY.target_pipe_1_1     Main|osc_clk_inferred_clock     FD1P3AX     Q       dataRXf_2[1]        1.348       986.854
stepperX.target_pipe_1_1     Main|osc_clk_inferred_clock     FD1P3AX     Q       target_pipe_1_1     1.348       986.854
stepperY.target_pipe_2_0     Main|osc_clk_inferred_clock     FD1P3AX     Q       target_pipe_2_0     1.348       986.854
stepperX.target_pipe_2_0     Main|osc_clk_inferred_clock     FD1P3AX     Q       dataRXf[2]          1.348       986.854
========================================================================================================================


Ending Points with Worst Slack
******************************

                      Starting                                                           Required            
Instance              Reference                       Type        Pin     Net            Time         Slack  
                      Clock                                                                                  
-------------------------------------------------------------------------------------------------------------
stepperX.curr[14]     Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[14]     1000.425     986.482
stepperY.curr[14]     Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[14]     1000.425     986.482
stepperX.curr[15]     Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[15]     1000.425     986.482
stepperY.curr[15]     Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[15]     1000.425     986.482
stepperY.curr[12]     Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[12]     1000.425     986.610
stepperX.curr[12]     Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[12]     1000.425     986.610
stepperX.curr[13]     Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[13]     1000.425     986.610
stepperY.curr[13]     Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[13]     1000.425     986.610
stepperY.curr[10]     Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[10]     1000.425     986.738
stepperX.curr[10]     Main|osc_clk_inferred_clock     FD1P3AX     D       curr_s[10]     1000.425     986.738
=============================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            -0.425
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.425

    - Propagation time:                      13.943
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     986.482

    Number of logic level(s):                18
    Starting point:                          stepperY.target_pipe_1_2 / Q
    Ending point:                            stepperY.curr[15] / D
    The start point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            Main|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                               Pin       Pin               Arrival     No. of    
Name                            Type         Name      Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
stepperY.target_pipe_1_2        FD1P3AX      Q         Out     1.720     1.720       -         
LED_cf_7[1]                     Net          -         -       -         -           8         
targetY_latmux                  ORCALUT4     A         In      0.000     1.720       -         
targetY_latmux                  ORCALUT4     Z         Out     0.337     2.057       -         
targetY[0]                      Net          -         -       -         -           6         
stepperY.target_2_0_cry_1_0     CCU2         B0        In      0.000     2.057       -         
stepperY.target_2_0_cry_1_0     CCU2         COUT1     Out     1.761     3.818       -         
target_2_0_cry_2                Net          -         -       -         -           1         
stepperY.target_2_0_cry_3_0     CCU2         CIN       In      0.000     3.818       -         
stepperY.target_2_0_cry_3_0     CCU2         S0        Out     1.970     5.787       -         
target[3]                       Net          -         -       -         -           3         
stepperY.state21_cry_2_0        CCU2         B1        In      0.000     5.787       -         
stepperY.state21_cry_2_0        CCU2         COUT1     Out     1.761     7.548       -         
state21_cry_3                   Net          -         -       -         -           1         
stepperY.state21_cry_4_0        CCU2         CIN       In      0.000     7.548       -         
stepperY.state21_cry_4_0        CCU2         COUT1     Out     0.128     7.676       -         
state21_cry_5                   Net          -         -       -         -           1         
stepperY.state21_cry_6_0        CCU2         CIN       In      0.000     7.676       -         
stepperY.state21_cry_6_0        CCU2         COUT1     Out     0.128     7.805       -         
state21_cry_7                   Net          -         -       -         -           1         
stepperY.state21_cry_8_0        CCU2         CIN       In      0.000     7.805       -         
stepperY.state21_cry_8_0        CCU2         COUT1     Out     0.128     7.933       -         
state21_cry_9                   Net          -         -       -         -           1         
stepperY.state21_cry_10_0       CCU2         CIN       In      0.000     7.933       -         
stepperY.state21_cry_10_0       CCU2         COUT1     Out     0.128     8.060       -         
state21_cry_11                  Net          -         -       -         -           1         
stepperY.state21_cry_12_0       CCU2         CIN       In      0.000     8.060       -         
stepperY.state21_cry_12_0       CCU2         COUT1     Out     0.128     8.188       -         
state21_cry_13                  Net          -         -       -         -           1         
stepperY.state21_cry_14_0       CCU2         CIN       In      0.000     8.188       -         
stepperY.state21_cry_14_0       CCU2         COUT1     Out     1.460     9.649       -         
curr_0                          Net          -         -       -         -           23        
stepperY.curr_cry_0[0]          CCU2         A0        In      0.000     9.649       -         
stepperY.curr_cry_0[0]          CCU2         COUT1     Out     1.761     11.410      -         
curr_cry[1]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[2]          CCU2         CIN       In      0.000     11.410      -         
stepperY.curr_cry_0[2]          CCU2         COUT1     Out     0.128     11.538      -         
curr_cry[3]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[4]          CCU2         CIN       In      0.000     11.538      -         
stepperY.curr_cry_0[4]          CCU2         COUT1     Out     0.128     11.666      -         
curr_cry[5]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[6]          CCU2         CIN       In      0.000     11.666      -         
stepperY.curr_cry_0[6]          CCU2         COUT1     Out     0.128     11.794      -         
curr_cry[7]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[8]          CCU2         CIN       In      0.000     11.794      -         
stepperY.curr_cry_0[8]          CCU2         COUT1     Out     0.128     11.922      -         
curr_cry[9]                     Net          -         -       -         -           1         
stepperY.curr_cry_0[10]         CCU2         CIN       In      0.000     11.922      -         
stepperY.curr_cry_0[10]         CCU2         COUT1     Out     0.128     12.050      -         
curr_cry[11]                    Net          -         -       -         -           1         
stepperY.curr_cry_0[12]         CCU2         CIN       In      0.000     12.050      -         
stepperY.curr_cry_0[12]         CCU2         COUT1     Out     0.128     12.178      -         
curr_cry[13]                    Net          -         -       -         -           1         
stepperY.curr_cry_0[14]         CCU2         CIN       In      0.000     12.178      -         
stepperY.curr_cry_0[14]         CCU2         S1        Out     1.766     13.943      -         
curr_s[15]                      Net          -         -       -         -           1         
stepperY.curr[15]               FD1P3AX      D         In      0.000     13.943      -         
===============================================================================================



##### END OF TIMING REPORT #####]

Constraints that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 144MB peak: 145MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 144MB peak: 145MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2280c-3

Register bits: 181 of 2280 (8%)
PIC Latch:       0
I/O cells:       18


Details:
CCU2:           93
FD1P3AX:        117
FD1P3AY:        2
FD1S3AX:        45
FD1S3AY:        1
FD1S3IX:        16
GSR:            1
IB:             1
INV:            8
OB:             12
OBZ:            5
ORCALUT4:       111
OSCC:           1
PUR:            1
VHI:            7
VLO:            7
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 53MB peak: 145MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Sun Sep 04 16:50:27 2016

###########################################################]