Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1368R, Built Jan  8 2016 09:37:50
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Product Version K-2015.09L-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

Linked File: PlotterV3_Imp_scck.rpt
Printing clock  summary report in "C:\Users\Zabrsa\Dropbox\FPGA\PlotterV3\PlotterV3_Imp\PlotterV3_Imp_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)

@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=3  set on top level netlist Main

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)



Clock Summary
*****************

Start                               Requested     Requested     Clock                                          Clock                
Clock                               Frequency     Period        Type                                           Group                
------------------------------------------------------------------------------------------------------------------------------------
Main|count_derived_clock[0]         1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Autoconstr_clkgroup_0
Main|osc_clk_inferred_clock         1.0 MHz       1000.000      inferred                                       Autoconstr_clkgroup_0
StepperTime_0|tmr_derived_clock     1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Autoconstr_clkgroup_0
StepperTime_1|tmr_derived_clock     1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Autoconstr_clkgroup_0
TimeRX|tmrRX_derived_clock          1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Autoconstr_clkgroup_0
UartRX|isBusy_derived_clock         1.0 MHz       1000.000      derived (from Main|osc_clk_inferred_clock)     Autoconstr_clkgroup_0
====================================================================================================================================

@W:MT529 : timerx.v(7) | Found inferred clock Main|osc_clk_inferred_clock which controls 53 sequential elements including uartRX1.timeRX1.c_delay[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N:MO111 : main.v(4) | Tristate driver sgnServo (in view: work.Main(verilog)) on net sgnServo (in view: work.Main(verilog)) has its enable tied to GND.

Available hyper_sources - for debug and ip models
	None Found

None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 140MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Sep 03 16:39:18 2016

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