Project Settings
Project Name proj_1 Implementation Name PlotterV3_Imp
Top Module Main Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 1000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 Clock Conversion 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 22 8 0 - 0m:01s - 4. 9. 2016
16:50:21
(premap)Complete 7 2 0 0m:00s 0m:00s 140MB 4. 9. 2016
16:50:23
(fpga_mapper)Complete 37 13 0 0m:03s 0m:03s 145MB 4. 9. 2016
16:50:27
Multi-srs Generator Complete4. 9. 2016
16:50:22

Area Summary
Register bits 181 I/O cells 18
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 111

Timing Summary
Clock NameReq FreqEst FreqSlack
Main|osc_clk_inferred_clock1.0 MHz74.0 MHz986.482

Optimizations Summary
Combined Clock Conversion 0 / 1